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IDT72V14320 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY - Integrated Device Technology

भाग संख्या IDT72V14320
समारोह 3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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<?=IDT72V14320?> डेटा पत्रक पीडीएफ

IDT72V14320 pdf
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
DESCRIPTION:
The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with independent clocked
read and write controls and high density offerings up to 1 Mbit.
Each FIFO has a data input port (Dn) and a data output port (Qn). The
frequencies of both the RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to fS(MAX) with complete independence.
There are no restrictions on the frequency oftheoneclockinputwithrespect
to the other.
These FIFOs have five flag pins,EF (Empty Flag),FF (FullFlag),HF(Half-
full Flag), PAE(Programmable Almost-Empty flag) and PAF(Programmable
Almost-Full flag).
PAE and PAFcan be programmed independently to switch at any point in
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
be loaded with the serial interface to any user desired value or by default values.
Eight default offset settings are provided, so thatPAEcan be set to switch at a
predefined number of locations from the empty boundary and the PAF threshold
canalsobesetatsimilarpredefinedvaluesfromthefullboundary. Thedefault
offset values are set during Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI).
During Master Reset (MRS) the read and write pointers are set to the first
location of the FIFO.
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
INDEX
WEN
SEN
DNC(1)
VCC
DNC(1)
GND
GND
D0
VCC
D1
GND
D2
D3
GND
D4
D5
D6
D7
D8
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NOTE:
1. DNC = Do Not Connect.
60 VCC
59 OE
58 VCC
57 Q0
56 Q1
55 GND
54 GND
53 DNC(1)
52 Q2
51 VCC
50 Q3
49 Q4
48 GND
47 Q5
46 GND
45 Q6
44 VCC
43 Q7
42 Q8
41 Q9
6163 drw02
TQFP (PN80-1, order code: PF)
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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT72V143203.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITYIntegrated Device Technology
Integrated Device Technology


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