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ISL6535 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Synchronous Buck Pulse-Width Modulator (PWM) Controller - Renesas

भाग संख्या ISL6535
समारोह Synchronous Buck Pulse-Width Modulator (PWM) Controller
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
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<?=ISL6535?> डेटा पत्रक पीडीएफ

ISL6535 pdf
ISL6535
Pin Descriptions
PIN #
SOIC
1
PIN #
QFN
14
2 15
31
42
53
64
76
87
98
10 9
11 10
12 11
13 12
14 13
-5
- 16
- PAD
PIN NAME
RT
OCSET
SS
COMP
FB
EN
GND
PHASE
UGATE
BOOT
PGND
LGATE
PVCC
VCC
REFIN
SSDONE
EPAD
DESCRIPTION
This pin provides oscillator switching frequency adjustment. By placing a resistor (RRT) from
this pin to GND, the switching frequency is set from between 200kHz and 1.5MHz according
Equation 1:
RRTk  -F---s------k---H-----z----6---5–---0--2--0-0---0-------k---H-----z----1.3k
(RRT to GND)
(EQ. 1)
Alternately ISL6535’s switching frequency can be lowered from 200kHz to 50kHz by
connecting the RT pin with a resistor to VCC according to Equation 2:
RRTk  2----0---0------k----H---5--z-5----0--–-0---F0----s------k---H-----z----+ 70k
(RRT to VCC)
(EQ. 2)
The current limit is programmed by connecting this pin with a resistor and capacitor to the
drain of the high-side MOSEFT. A 200µA current source develops a voltage across the
resistor, which is then compared with the voltage developed across the high-side MOSFET. A
blanking period of 120ns is provided for noise immunity.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 30µA
current source, sets the soft-start interval of the converter.
COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting
input of the error amplifier and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-control feedback loop of the converter.
This pin is a TTL compatible input. Pull this pin below 0.8V to disable the converter. In
shutdown the soft-start pin is discharged and the UGATE and LGATE pins are held low.
Signal ground for the IC. All voltage levels are measured with respect to this pin.
This pin connects to the source of the high-side MOSFET and the drain of the low-side
MOSFET. This pin represents the return path for the high-side gate driver. During normal
switching, this pin is used for high-side current sensing.
Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper
MOSFET.
This pin provides bias to the upper MOSFET driver. A bootstrap circuit may be used to create
a BOOT voltage suitable to drive a standard N-channel MOSFET.
This is the power ground connection. Tie the lower MOSFET source and board ground to this
pin.
Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower
MOSFET.
Provide a 12V ±10% bias supply for the lower gate drive to this pin. This pin should be
bypassed with a capacitor to PGND.
Provide a 12V bias supply for the chip to this pin. The pin should be bypassed with a capacitor
to GND.
Upon enable if REFIN is less than 2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. An internal 6µA pull-up to 5V is provided
for disabling this functionality.
Provides an open-drain signal at the end of soft-start.
The exposed pad is at GND potential, but does not conduct current; the GND and PGND pins
must be used for bias current. The pad should be tied to a GND plane with as many thermal
vias as possible, for optimal thermal performance.
FN9255 Rev 3.00
March 3, 2016
Page 2 of 15

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