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ISL24212 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Vcom Calibrator - Renesas

भाग संख्या ISL24212
समारोह Programmable Vcom Calibrator
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
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ISL24212 pdf
ISL24212
Block Diagram
VDD
6
AVDD
3
DNC 4
CTL 7
CE 8
DIGITAL UP/DOWN
DAC
INTERFACE COUNTER REGISTERS
8-Bit EEPROM
CS
ANALOG DCP
AND
CURRENT SINK
Q1
A1
Pin Configuration
5
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24212
ISL24212
(10 LD TDFN)
TOP VIEW
VCOM BUFFER
AMPLIFER
2
DVR_OUT
10
A2 VCOM_OUT
1
INN
9
SET
INN 1
DVR_OUT 2
AVDD 3
DNC 4
GND 5
10 VCOM_OUT
EXPOSED
THERMAL
PAD*
9 SET
8 CE
7 CTL
6 VDD
(*CONNECT THERMAL PAD TO GND)
Pin Descriptions
PIN PIN
NAME NUMBER
FUNCTION
INN
DVR_OUT
1 Negative input of the op amp. To create a unity-gain VCOM voltage buffer, connect this pin to the VCOM_OUT pin.
2 Current Sink Output. The sink current into the DVR_OUT (Digital Variable Resistor) pin is equal to the DAC setting times the maximum
adjustable sink current divided by 256. See the “SET” pin function description (pin 9) for setting the maximum adjustable sink
current.
AVDD
DNC
3 High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
4 Do Not Connect to external circuitry. It is acceptable to ground this pin.
GND 5 Ground connection.
VDD 6 Digital power supply input. Bypass to GND with 0.1µF capacitor.
CTL 7 Up/Down Control for internal counter and Internal EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter, adding 1 to the DAC setting, increasing the DVR_OUT sink current, and
lowering the divider voltage at the DVR_OUT pin.
A high-to-mid transition decrements the 8-bit counter, subtracting 1 from the DAC setting, decreasing the DVR_OUT sink current,
and increasing the divider voltage at the DVR_OUT pin.
To program the EEPROM, take this pin to >4.9V (see “CTL EEPROM Programming Signal Time” in the “Electrical Specification”
table on page 5 for details). Float when not in use.
FN7590 Rev 0.00
March 15, 2011
Page 2 of 12

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डाउनलोड[ ISL24212 Datasheet.PDF ]


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