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ISL22317 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Precision Single Digitally Controlled Potentiometer - Renesas

भाग संख्या ISL22317
समारोह Precision Single Digitally Controlled Potentiometer
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
1 Page
		
<?=ISL22317?> डेटा पत्रक पीडीएफ

ISL22317 pdf
ISL22317
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL22317TFRTZ
317T
100
-40 to +125
10 Ld TDFN
L10.3x3B
ISL22317UFRTZ
317U
50
-40 to +125
10 Ld TDFN
L10.3x3B
ISL22317WFRTZ
317W
10
-40 to +125
10 Ld TDFN
L10.3x3B
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL22317. For more information on MSL please see techbrief
TB363.
Block Diagram
VCC
SCL
SDA
A1
RREF
10k0.5%
External Resistor
for W option,
or 50k0.5%
for U and T options
respectively
REF_A
REF_B
Pinout
ISL22317
(10 LD TDFN)
TOP VIEW
SCL 1
SDA 2
A1 3
REF_A 4
REF_B 5
10 VCC
9 RH
8 RW
7 RL
6 GND
FN6912 Rev 1.00
April 15, 2010
POWER-UP,
INTERFACE,
EEPROM
AND
CONTROL
LOGIC
RH
RW
RL
GND
Pin Descriptions
TDFN
PIN #
1
2
3
SYMBOL
SCL
SDA
A1
DESCRIPTION
Open drain I2C interface clock input
Open drain Serial data I/O for the I2C interface
Device address input for the I2C interface
4 REF_A Terminal A for an external reference resistor
5 REF_B Terminal B for an external reference resistor
6 GND Device ground pin
7 RL “Low” terminal of DCP
8 RW “Wiper” terminal of DCP
9 RH “High” terminal of DCP
10 VCC Power supply pin
EPAD* Exposed Die Pad internally connected to
GND
*PCB thermal land for QFN/TDFN EPAD should be connected to
GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
Page 2 of 15

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