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IDT71V547XS डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V Synchronous SRAM - IDT

भाग संख्या IDT71V547XS
समारोह 3.3V Synchronous SRAM
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT71V547XS?> डेटा पत्रक पीडीएफ

IDT71V547XS pdf
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBTFeature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,
or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
The IDT71V547 contains address, data-in and control signal regis-
ters. Theoutputsareflow-through(nooutputdataregister).Outputenable
is the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
when ADV/LDis low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBO input
pin. The LBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A0 - A16
Address Inputs
CE1, CE2, CE2
Three Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2, BW3, BW4 Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address / Load New Address
LBO Linear / Interleaved Burst Order
I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output
VDD 3.3V Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3822 tbl 01
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT71V547XS3.3V Synchronous SRAMIDT
IDT


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