DataSheet.in

IDT71T75902 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V Synchronous ZBT SRAM - IDT

भाग संख्या IDT71T75902
समारोह 2.5V Synchronous ZBT SRAM
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT71T75902?> डेटा पत्रक पीडीएफ

IDT71T75902 pdf
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Description
The IDT71T75902 is a 2.5V high-speed 18,874,368-bit (18 Megabit)
synchronous SRAM organized as 1M x 18. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
orwritesandreads.Thusithas beengiventhenameZBTTM, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle occurs,
be it read or write.
The IDT71T75902 contain address, data-in and control signal regis-
ters. The outputs are flow-through (no output data register). Output enable
is the only asynchronous signal and can be used to disable the outputs
at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75902 to be
suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
Commercial and Industrial Temperature Ranges
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75902 has an on-chip burst counter. In the burst mode,
the IDT71T75902 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. TheLBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71T75902 SRAM utilize IDT’s high-performance CMOS
process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Pin Description Summary
A0-A19
Address Inputs
CE1, CE2, CE2
Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2
Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address/Load New Address
LBO Linear/Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP2
Data Input/Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5319 tbl 01a
6.422

विन्यास 23 पेज
डाउनलोड[ IDT71T75902 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT71T759022.5V Synchronous ZBT SRAMIDT
IDT


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English