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IDT72V2101 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS FIFO memories - IDT

भाग संख्या IDT72V2101
समारोह CMOS FIFO memories
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=IDT72V2101?> डेटा पत्रक पीडीएफ

IDT72V2101 pdf
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from
0 to fMAX with complete independence. There are no restrictions on the
frequency of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsistsofactivating RENandenablinga
risingRCLKedge,willshiftthewordfrominternalmemorytothedataoutputlines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for access.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FFfunctionsareselectedinIDTStandardmode. The IRand ORfunctionsare
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PIN CONFIGURATIONS
PIN 1
WEN
SEN
DC(1)
VCC
VCC
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
Q7
Q6
GND
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
TQFP (PN64, order code: PF)
TOP VIEW
2
4669 drw 02

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