IDT8V89317 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - 10G Ethernet PLL and IEEE 1588 Synthesizer - IDT

भाग संख्या IDT8V89317
समारोह 10G Ethernet PLL and IEEE 1588 Synthesizer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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IDT8V89317 pdf
The IDT8V89317 10G Ethernet PLL for Industrial Automation and
Power Systems is used to synchronize equipment with synchronization
sources using the Ethernet physical layer, or with a 1 PPS (1 Hz) GPS
clock; it can also be used by external IEEE 1588 clock recovery servos
to synthesize IEEE 1588 clocks. The IDT8V89317 ultra-low jitter output
clocks can be used to directly synchronize 10GBASE-R Ethernet PHYs
and XAUI or QSGMII devices.
The IDT8V89317 synchronization functions are provided by a Digital
PLL (DPLL) with an embedded clock synthesizer. The DPLL accepts
three single ended reference inputs that can operate at 1PPS (1 Hz), 25
MHz, 125 MHz or 156.25 MHz. The references are continually moni-
tored for loss of signal and for frequency offset per user programmed
thresholds. The active reference for the DPLL is determined by forced
selection or by automatic selection based on user programmed priorities
and locking allowances and based on the reference monitors.
The DPLL supports four primary operating modes: Free-Run,
Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In
Free-Run mode the DPLL generates a clock based on the master clock
alone. In Locked mode the DPLL filters reference clock jitter with the
selected bandwidth. In Locked mode the long-term DPLL frequency
accuracy is the same as the long term frequency accuracy of the
selected input reference. In Holdover mode the DPLL uses frequency
data acquired while in Locked mode to generate accurate frequencies
when input references are not available. In DCO Control Mode the DPLL
control loop is opened and the DCO can be used by an algorithm (e.g.
IEEE 1588 clock servo) running on an external processor to synthesize
clock signals.
The IDT8V89317 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLL in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLL in Free-Run mode and in Holdover mode.
The master clock must be sufficiently stable to support the selected
DPLL filtering bandwidth; in particular, the 15 mHz bandwidth requires a
very stable temperature compensated crystal oscillator (TCXO) or ove-
nized crystal oscillator (OCXO). Refer to the IDT application note “Rec-
ommended Crystal Oscillators for IDT’s Network Synchronization WAN-
PLLTM” for guidance.
The DPLL can be configured with a filtering bandwidth of 15 mHz or
1.2 Hz. The 15 mHz bandwidth can be used to lock the DPLL directly to
a 1 pulse per second (PPS) reference. 1.2 Hz bandwidth can be used to
lock to Ethernet connected synchronization sources operating at 25
MHz, 125 MHz or 156.25 MHz.
The clock synthesized by the IDT8V89317 DPLL is passed through
two independent voltage controlled crystal oscillator (VCXO) based jitter
attenuating analog PLLs (APLLs). The APLLs drive independent divid-
ers that have differential outputs. The APLLs use external crystal reso-
nators with resonant frequencies equal to the APLL base frequency
divided by 25. The output clocks generated by the APLLs exhibit jitter
below 0.30ps RMS over the integration range 10 kHz to 20 MHz.
The IDT8V89317 generates a 25 MHz single ended output that is
based on the free running 12.8 MHz master clock. The frequency accu-
racy and the frequency stability of this 25 MHz clock are determined by
the master clock.
2 May 5, 2014

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डाउनलोड[ IDT8V89317 Datasheet.PDF ]

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भाग संख्याविवरणविनिर्माण
IDT8V89316Ethernet PLL and IEEE 1588 SynthesizerIDT
IDT8V8931710G Ethernet PLL and IEEE 1588 SynthesizerIDT

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