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IDT8V89316 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Ethernet PLL and IEEE 1588 Synthesizer - IDT

भाग संख्या IDT8V89316
समारोह Ethernet PLL and IEEE 1588 Synthesizer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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IDT8V89316 pdf
IDT8V89316 DATASHEET
ETHERNET PLL AND IEEE 1588 SYNTHESIZER FOR INDUSTRIAL AUTOMATION AND POWER SYSTEMS
DESCRIPTION
The IDT8V89316 Ethernet PLL for Industrial Automation and Power
Systems is used to synchronize equipment with synchronization sources
using the Ethernet physical layer; it can also be used by external IEEE
1588 clock recovery servos to synthesize IEEE 1588 clocks. The
IDT8V89316 low jitter output clocks can be used to directly synchronize
1 Gigabit Ethernet PHYs and QSGMII devices.
The IDT8V89316 synchronization functions are provided by a Digital
PLL (DPLL) with an embedded clock synthesizer. The DPLL accepts
three single ended reference inputs that can operate at 25 MHz, 125
MHz or 156.25 MHz. The references are continually monitored for loss
of signal and for frequency offset per user programmed thresholds. The
active reference for the DPLL is determined by forced selection or by
automatic selection based on user programmed priorities and locking
allowances and based on the reference monitors.
The DPLL supports four primary operating modes: Free-Run,
Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In
Free-Run mode the DPLL generates a clock based on the master clock
alone. In Locked mode the DPLL filters reference clock jitter with the
selected bandwidth. In Locked mode the long-term DPLL frequency
accuracy is the same as the long term frequency accuracy of the
selected input reference. In Holdover mode the DPLL uses frequency
data acquired while in Locked mode to generate accurate frequencies
when input references are not available. In DCO Control Mode the DPLL
control loop is opened and the DCO can be used by an algorithm
(e.g. IEEE 1588 clock servo) running on an external processor to syn-
thesize clock signals.
The IDT8V89316 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLL in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLL in Free-Run mode and in Holdover mode.
Refer to the IDT application note “Recommended Crystal Oscillators for
IDT’s Network Synchronization WAN-PLLTM” for guidance.
The clock synthesized by the IDT8V89316 DPLL is passed through a
voltage controlled crystal oscillator (VCXO) based jitter attenuating ana-
log PLL (APLL). The APLL drives independent dividers that have differ-
ential outputs. The APLL uses an external crystal resonator with
resonant frequencies equal to the APLL base frequency divided by 25.
The output clocks generated by the APLL exhibits jitter below 0.65ps
RMS over the integration range 10 kHz to 20 MHz.
The IDT8V89316 generates a 25MHz single ended output that is
based on the free running 12.8 MHz master clock. The frequency accu-
racy and the frequency stability of this 25 MHz clock are determined by
the master clock.
Description
2 May 5, 2014
IDT CONFIDENTIAL

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