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IDT8P34S1212I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1:12 LVDS Output 1.8V Fanout Buffer - IDT

भाग संख्या IDT8P34S1212I
समारोह 1:12 LVDS Output 1.8V Fanout Buffer
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IDT8P34S1212I pdf
IDT8P34S1212I Datasheet
Pin Descriptions and Characteristics
Table 1. Pin DescriptionsNote 1.
Number
Name
Type
Description
1
SEL
Input
Pulldown
Reference select control. See Table 3 for function.
LVCMOS/LVTTL interface levels.
2
CLK1
Input
Pulldown Non-inverting differential clock/data input.
3
nCLK1
Input
Pulldown/
Pullup
Inverting differential clock/data input.
4, 10
nc Unused
Do not connect.
5, 6, 11, 20,
31, 40
7
8
VDD
VREF
nCLK0
Power
Input
Pulldown/
Pullup
Power supply pins.
Bias voltage reference. Provides an input bias voltage for the CLKx, nCLKx
input pairs in AC-coupled applications. Refer to Figures 2B and 2C for
applicable AC-coupled input interfaces.
Inverting differential clock/data input.
9
CLK0
Input
Pulldown Non-inverting differential clock/data input.
12, 13
Q0, nQ0
Output
Differential output pair 0. LVDS interface levels.
14, 15
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
16, 17
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
18, 19
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
21, 30
GND
Power
Power supply ground.
22, 23
Q4, nQ4
Output
Differential output pair 4. LVDS interface levels.
24, 25
Q5, nQ5
Output
Differential output pair 5. LVDS interface levels.
26, 27
Q6, nQ6
Output
Differential output pair 6. LVDS interface levels.
28, 29
Q7, nQ7
Output
Differential output pair 7. LVDS interface levels.
32, 33
Q8, nQ8
Output
Differential output pair 8. LVDS interface levels.
34, 35
Q9, nQ9
Output
Differential output pair 9. LVDS interface levels.
36, 37
Q10, nQ10
Output
Differential output pair 10. LVDS interface levels.
38, 39
Q11, nQ11
Output
Differential output pair 11. LVDS interface levels.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function TableNote 1.
Input
SEL Operation
0 (Default) CLK0, nCLK0 is the selected differential clock input.
1 CLK1, nCLK1 is the selected differential clock input.
1. SEL is an asynchronous control.
©2017 Integrated Device Technology, Inc.
2
November 24, 2017

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