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डेटा पत्रक - 1:4 LVDS Output 1.8V Fanout Buffer - IDT

भाग संख्या IDT8P34S1204I
समारोह 1:4 LVDS Output 1.8V Fanout Buffer
मैन्युफैक्चरर्स IDT 
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IDT8P34S1204I pdf
IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin DescriptionsNote1.
Number
Name
Type
1
GND
Power
Description
Power supply ground.
2
SEL
Input
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
3
CLK1
Input
Pulldown Non-inverting differential clock/data input.
4
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
5 VDD Power
Power supply pin.
6
CLK0
Input
Pulldown Non-inverting differential clock/data input.
7
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
8
VREF
Output
Bias voltage reference. Provides an input bias voltage for the
CLK[0:1], nCLK[0:1] input pairs in AC-coupled applications. Refer to
Figures 2B and 2C for applicable AC-coupled input interfaces.
9, 10
Q0, nQ0
Output
Differential output pair 0. LVDS interface levels.
11, 12
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
13, 14
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
15, 16
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function TableNote1.
Input
SEL
0 (default)
Operation
CLK0, nCLK0 is the selected differential clock input.
1 CLK1, nCLK1 is the selected differential clock input.
1. SEL is an asynchronous control.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
2
©2014 Integrated Device Technology, Inc.

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IDT8P34S1204I1:4 LVDS Output 1.8V Fanout BufferIDT
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