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Am1407 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Dual 100-Bit Dynamic Shift Registers - AMD

भाग संख्या Am1407
समारोह Dual 100-Bit Dynamic Shift Registers
मैन्युफैक्चरर्स AMD 
लोगो AMD लोगो 
पूर्व दर्शन
1 Page
		
<?=Am1407?> डेटा पत्रक पीडीएफ

Am1407 pdf
Am14/1506· Am14/1507
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Power Dissipation
Data and Clock Input Voltages with respect to most Positive Supply Voltage, Vee
Power Supply Voltage, VDD with respect to Vee
500mW
+0.5 V to -25 V
+0.5 V to -25 V
ELECTRICAL CHARACTERISTICS Am1506/1507 TA= OOC to +70oC } unless otherwise specified
Am1406/1407 TA = -55°C to +1250 C
DC Characteristics Over Operating Temperature Range (VDD = -5.0 V ±5%,Vee= +5.0 V ±5% unless otherwise specified)
Limits Over Specified Temperature Range
Parameters
Test Conditions
Min.
Typ. (Note 1)
Max.
Units
VOH (Note 2)
Output HIGH
Voltage
IOH = -2.5 mA
Load = 20 kn
2.5 4.0
Volts
VOL (Note 2)
Output LOW
Voltage
IOL = 200 /LA
1407,1507 only
-1.2
0.4
Volts
VIH
Input HIGH
Voltage
VDD = -5.0 V
Vee = +5.0 V
2.5 5.0 5.3 Volts
V IL
Input LOW
Voltage
VDD = -5.0 V
Vee = +5.0 V
-10
0.2
0.8
Volts
V IHC
Clock
Input HIGH
Voltage
VDD = -5.0 V
Vee = +5.0V
3.5 5.3 Volts
V ILC
Clock
Input LOW
Voltage
VDD = -5.0 V
Vee = +5.0 V
-13
-9.5
Volts
IL
Input Load
Current
Input Pin 1
Input Pin 7
Pins 2, 3, 4, 5, 6, 7 = 0 V
Pin1=-18V Pin 8 = -8 V
Pins 1, 2, 3, 4, 5, 6 = 0 V
Pin7=-18V Pin 8 = -8 V
TA= 25°C
TA= 25°C
500 nA
ILC
Clock Input
Current
Clock Input Pins 3,5 = -18 V
All Other Pins = 0 V
TA =25°C
500 nA
ILO (Note 3)
Output
Leakage
Current
Output Pin 2
Output Pin 6
Pins 1, 4, 6, 7, 8 = 0 V
Pin2=-18V Pins 3, 5 = -8 V
Pins1,2,4,7,8=OV
Pin6=-18V Pins 3, 5 = -8 V
500 nA
IDO (See Graphs)
Power
Supply (Note 4)
Current
f = 1MHz
Duty Cycle = 60%
TA = 25°C
TA = OOC
TA = -55°C
4.0 8.0
5.0 10 mA
8.0 13
Zout
Output ON
Impedance
CIN
Input
*
Capacitance
Clock
Input
Capacitance
*
Cout (Note 4) *
Output
Capacitance
VDD = -5.0 V IOH = -2.5 mA
Vee = +5.0 V
Input Pins 1, 7
Vltj = Vee
Clock Input Pins 3, 5 V¢ = Vee
Clock Input Pins 3, 5 V¢ = -20 V Bias
Output Pins 2, 6
Vout = Vee
300 750 n
4 pF
40
pF
35
5 pF
Note 1: Typical values are at Vee - VDD = 10 V and TA = 25°C.
Note 2: In the logic HIGH level the MaS register output can supply 2.5 mA Into the load combination of the internal pull-down resistor and the external load. In
logic LOW level, IOL represents the current the internal 20 kO resistor will sink. In order to insure current sinking capability for one standard TTL load, an external p
down resistor must be added. See applications.
Note 3: Leakage current for 1406 and 1506 only. For 1407 and 1507 the output on pins 2 and 6 will exhibit a resistance when measured with thE!" following bias c
ditions: pins 1, 6, and 8 at GND; pins 3 and 5 at -16 V; pin 4 open; measure pins 2 and 6. 25 kO:2: ROUT :2: 15 kO.
Nole 4: Power dissipation Is directly proportional to clock duty cycle. Duty cycle Is defined as: clock frequency (t¢,pw + t¢2PW + 112 [Ir + If))'
*This paramenler is periodically sampled and is nol 1000/0 tesled.
5-2

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