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DSC2231 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS Oscillator - Discera

भाग संख्या DSC2231
समारोह Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS Oscillator
मैन्युफैक्चरर्स Discera 
लोगो Discera लोगो 
पूर्व दर्शन
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<?=DSC2231?> डेटा पत्रक पीडीएफ

DSC2231 pdf
DSC2131 DSC2231
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
SCLK
GND
SDA
MOSI
SCL
MISO
CS_bar
SS
Output1+
Output1-
NC
Output 2+
VDD2
VDD
FS
Pin Type
I
NA
NA
I
Power
I
I
O
I
I
O
O
NA
O
Power
Power
I
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
DSC2131: Leave unconnected or grounded
DSC2231: Serial clock from master
Ground
DSC2131: I2C Serial Data
DSC2231: SPI Serial Data from Master to Slave
DSC2131: I2C Serial Clock
DSC2231: SPI Serial Data from Slave to Master
DSC2131: I2C Chip Select (Active Low)
DSC2231: SPI Slave Select (Active Low)
Positive LVDS Output
Negative LVDS Output
Leave unconnected or grounded
CMOS Output
Power Supply for CMOS Output
Power Supply
Default output clock frequency bit
Operational Description
The DSC2131/2231 is a dual LVDS oscillator
consisting of a MEMS resonator and a support
PLL IC. The outputs are generated through
independent 8-bit programmable dividers from
the output of the internal PLL.
DSC2131/2231 allows for easy programming
of the output frequencies using I2C/SPI
interface. Upon power-up, the initial output
frequencies are controlled by an internal pre-
programmed memory (OTP). This memory
stores all coefficients required by the PLL for
two different default frequency pairs. The
control pin (FS) selects the initial pair. Once
the device is powered up, a new output
frequency pair can be programmed.
Programming details are provided in the
Programming Guide. Standard default
frequency pairs are described in the following
sections. Discera supports customer defined
versions of the DSC2131/2231.
When Enable (pin 1) is floated or connected to
VDD, the DSC2131/2231 is in operational
mode. Driving Enable to ground will tri-state
both output drivers (hi-impedance mode).
The DSC2131/2231 has programmable CMOS
output drive strength, which can be controlled
via I2C/SPI. Table 1 displays typical rise / fall
times for the output with a 15pf load
capacitance as a function of these control bits
at VDD=3.3V and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OXS2, OXS1, OXS0] - Default [111]
X=1 for output1, and 2 for output2
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
tf (ns) 2.5 2.4 2.4 2 1.8 1.6 1.3 1.3
VDD2 supply the CMOS output and must be
equal to or less than VDD. VDD2 can be as
low as 1.65V.
_____________________________________________________________________________________________________________________________ _________________
DSC2131 DSC2231
Page 2
MK-Q-B-P-D-12050107

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