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DSC2021 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low-Jitter Configurable Dual LVPECL-CMOS Oscillator - Discera

भाग संख्या DSC2021
समारोह Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
मैन्युफैक्चरर्स Discera 
लोगो Discera लोगो 
पूर्व दर्शन
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<?=DSC2021?> डेटा पत्रक पीडीएफ

DSC2021 pdf
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
OS0
GND
FS0
FS1
FS2
Output1+
Output1-
OS1
Output 2
VDD2
VDD
OS2
Pin
Type
I
NA
I
Power
I
I
I
O
O
I
O
Power
Power
I
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Least significant bit for output drive strength selection for CMOS
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Power Supply
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2021 is a dual output LVPECL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
LVPECL, are generated through independent
8-bit programmable dividers from the output
of the internal PLL. Two constraints are
imposed on the output frequencies: 1) f2=M x
f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 <
1.7GHz.
The actual frequencies output by the DSC2021
are controlled by an internal pre-programmed
memory (OTP). This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 FS2) select the output
frequency combination. Discera supports
customer defined versions of the DSC2021.
Standard frequency options are described in in
the following sections.
The DSC2021 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2021 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2021 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
tf (ns) 2.5 2.4 2.4 2 1.8 1.6 1.3 1.3
_____________________________________________________________________________________________________________________________ _________________
DSC2021
Page 2
MK-Q-B-P-D-12042604-2

विन्यास 6 पेज
डाउनलोड[ DSC2021 Datasheet.PDF ]


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