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IDT71V35761SA डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V Synchronous SRAMs - IDT

भाग संख्या IDT71V35761SA
समारोह 3.3V Synchronous SRAMs
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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IDT71V35761SA pdf
IDT71V357611,1 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
controlregisters. InternallogicallowstheSRAMtogenerateaself-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating
the access sequence. The first cycle of output data will be pipelined
for one cycle before it is available on the next rising clock edge. If
burst mode operation is selected (ADV=LOW), the subsequent
three cycles of output data will be available to the user on the next
three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V35761 SRAMs utilize a high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array(fBGA).
Pin Description Summary
A0-A17
Address Inputs
CE Chip Enable
CS0, CS1
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5301 tbl 01
6.422

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT71V35761S3.3V Synchronous SRAMsIDT
IDT
IDT71V35761SA3.3V Synchronous SRAMsIDT
IDT


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