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8L30110 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Crystal or Differential to LVCMOS/LVTTL Clock Buffer - IDT

भाग संख्या 8L30110
समारोह Crystal or Differential to LVCMOS/LVTTL Clock Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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8L30110 pdf
8L30110 Datasheet
Pin Characteristics
Table 1. Pin Descriptions[a]
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ePad
Name
Q0
VDDO
Q1
GNDO
Q2
VDDO
Q3
Q4
GNDO
VDD
XTAL_IN
XTAL_OUT
CLK0
nCLK0
GND
GNDO
Q5
Q6
VDDO
Q7
GNDO
Q8
VDDO
Q9
GNDO
GND
nCLK1
CLK1
SEL1
SEL0
OE
GNDO
GND_EP
Type
Output
Power
Output
Power
Output
Power
Output
Output
Power
Power
Input
Output
Input
Pulldown
Input
Pullup/
Pulldown
Power
Power
Output
Output
Power
Output
Power
Output
Power
Output
Power
Power
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Power
Power
Pulldown
Description
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Power supply.
Crystal input.
Crystal output.
Non-inverting differential clock.
Inverting differential clock. Internal resistor bias to VDD/2.
Power supply core ground.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Power supply core ground.
Inverting differential clock. Internal resistor bias to VDD/2.
Non-inverting differential clock.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable. LVCMOS/LVTTL interface levels. See Table
3B.
Power supply output ground.
Exposed pad of package. Connect to ground.
[a] Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2018 Integrated Device Technology, Inc.
2
April 11, 2018

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