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IDT8T73S208I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVPECL Clock Divider and Fanout Buffer - IDT

भाग संख्या IDT8T73S208I
समारोह LVPECL Clock Divider and Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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IDT8T73S208I pdf
IDT8T73S208I Data Sheet
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND FANOUT BUFFER
Table 1. Pin Descriptions
Number
1,
32
2, 7, 18, 23
3, 4
5, 6
8, 17
9, 10
11, 12
13, 14
15, 16
19, 20
21, 22
24,
25
26
27
28
29
30
31
Name
ADR1,
ADR0
VEE
Q0, nQ0
Q1, nQ1
VCCO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL0,
FSEL1
IN
VT
nIN
VCC
SDA
SCL
Type
Description
Input
Pulldown I2C Address inputs. LVCMOS/LVTTL interface levels.
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Input
Termination
Input
Input
Power
I/O
Input
Pulldown
Pullup
Pullup
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Output supply pins.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
Differential output pair 6. LVPECL interface levels.
Differential output pair 7. LVPECL interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input. RT = 50termination to VT.
Input for termination. Both IN and nIN inputs are internally terminated 50to this
pin. See input termination information in the applications section.
Inverting differential clock input. RT = 50termination to VT.
Power supply pin.
I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output: open
drain.
I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
IDT8T73S208BNLI REVISION A OCTOBER 21, 2011
2
©2011 Integrated Device Technology, Inc.

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