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IDT8SLVP2102I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVPECL Output Fanout Buffer - IDT

भाग संख्या IDT8SLVP2102I
समारोह LVPECL Output Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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IDT8SLVP2102I pdf
IDT8SLVP2102I Data Sheet
LOW PHASE NOISE, DUAL 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1 VEE Power
2 nc Unused
Negative supply pin.
Do not connect.
3
PCLKB
Input
Pulldown Non-inverting differential LVPECL clock/data input.
4
nPCLKB
Input
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. VCC/2 default when left
floating.
5 VCC Power
Power supply pins.
6
PCLKA
Input
Pulldown Non-inverting differential LVPECL clock/data input.
7
8
9, 10
nPCLKA
VREF
QA0, nQA0
Input
Output
Output
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. VCC/2 default when left
floating.
Bias voltage reference for the PCLK, nPCLK inputs.
Differential output pair A0. LVPECL interface levels.
11, 12
QA1, nQA1
Output
Differential output pair A1. LVPECL interface levels.
13, 14
QB0, nQB0
Output
Differential output pair B0. LVPECL interface levels.
15, 16
QB1, nQB1
Output
Differential output pair B1. LVPECL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014
2
©2014 Integrated Device Technology, Inc.

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