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IDT8SLVP1212I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVPECL Output Fanout Buffer - IDT

भाग संख्या IDT8SLVP1212I
समारोह LVPECL Output Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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IDT8SLVP1212I pdf
IDT8SLVP1212I Data Sheet
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
2
3
4, 10
5, 6, 11, 20,
31, 40
7
8
SEL
PCLK1
nPCLK1
nc
VCC
VREF
nPCLK0
Input
Input
Input
Unused
Power
Output
Input
Pulldown
Pulldown
Pulldown/Pullup
Reference select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Non-inverting LVPECL differential clock/data input.
Inverting LVPECL differential clock/data input.
Do not connect.
Power supply pins.
Bias voltage reference.
Pulldown/Pullup Inverting LVPECL differential clock/data input.
9
12, 13
14, 15
16, 17
PCLK0
Q0, nQ0
Q1, nQ1
Q2, nQ2
Input
Output
Output
Output
Pulldown
Non-inverting LVPECL differential clock/data input.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Differential output pair 2. LVPECL interface levels.
18, 19
Q3, nQ3
Output
Differential output pair 3. LVPECL interface levels.
21, 30
22, 23
24, 25
VEE
Q4, nQ4
Q5, nQ5
Power
Output
Output
Negative power supply pins.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
26, 27
Q6, nQ6
Output
Differential output pair 6. LVPECL interface levels.
28, 29
32, 33
34, 35
36, 37
Q7, nQ7
Q8, nQ8
Q9, nQ9
Q10, nQ10
Output
Output
Output
Output
Differential output pair 7. LVPECL interface levels.
Differential output pair 8. LVPECL interface levels.
Differential output pair 9. LVPECL interface levels.
Differential output pair 10. LVPECL interface levels.
38, 39
Q11, nQ11
Output
Differential output pair 11. LVPECL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Section Function Table
Input
SEL Operation
0 (default) PCLK0, nPCLK0 is the selected differential clock input
1 PCLK1, nPCLK1 is the selected differential clock input
NOTE: SEL is an asynchronous control.
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
2
©2014 Integrated Device Technology, Inc.

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