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8SLVD1204-33 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVDS Output Fanout Buffer - IDT

भाग संख्या 8SLVD1204-33
समारोह LVDS Output Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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8SLVD1204-33 pdf
8SLVD1204-33 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
Power supply ground.
2
SEL
Input
Pullup/
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
3
PCLK1
Input
Pulldown Non-inverting differential clock/data input.
4
nPCLK1
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
5 VDD Power
Power supply pin.
6
PCLK0
Input
Pulldown Non-inverting differential clock/data input.
7
nPCLK0
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
8
9, 10
VREF
Q0, nQ0
Output
Output
Bias voltage reference for the PCLKx, nPCLKx inputs.
Differential output pair 0. LVDS interface levels.
11, 12
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
13, 14
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
15, 16
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL Operation
0 PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
Open (default)
Internally set to VDD/2.
Input buffers are disabled and outputs are static.
NOTE: SEL is an asynchronous control.
8SLVD1204-33 November 29, 2018
2 ©2018 Integrated Device Technology, Inc.

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
8SLVD1204-33LVDS Output Fanout BufferIDT
IDT


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