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8S89834I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer - IDT

भाग संख्या 8S89834I
समारोह 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8S89834I pdf
8S89834I Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
7, 14
8
9
10
11
12
13
15, 16
Vcc
EN
IN2
nc
SEL
IN1
VEE
Q0, nQ0
Power
Input
Input
Unused
Input
Input
Power
Output
Pullup
Pullup
Pullup
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a
37kpullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN1, IN2.
LVTTL/LVCMOS interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Select clock input. When LOW, selects IN2 and when HIGH selects IN1.
LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2016 Integrated Device Technology, Inc
2
Revision A January 27, 2016

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8S89834I2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock MultiplexerIDT
IDT


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