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डेटा पत्रक - 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination - IDT

भाग संख्या 8S89833
समारोह 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8S89833 pdf
8S89833 Data Sheet
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
3, 4 Q1, nQ1
5, 6
7, 14
8
9
10
11
12
13
15, 16
Q2, nQ2
VDD
EN
nIN
VREF_AC
VT
IN
GND
Q3, nQ3
Type
Output
Output
Output
Power
Input
Input
Output
Pullup
Input
Input
Power
Output
Description
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
Power supply pins.
Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables
outputs. Internally connected to a 37kpullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications. Equal to VDD - 1.4V (approx.). Maximum
sink/source current is ±2mA.
Input termination center-tap. Each side of the differential input pair terminates to a VT pin.
The VT pins provide a center-tap to a termination network for maximum interface flexibility.
Non-inverting differential clock input. RT = 50termination to VT.
Power supply ground.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2016 Integrated Device Technology, Inc
2
Revision B August 24, 2016

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