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8S89832I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1-to-4 Differential-to-LVDS Fanout Buffer - IDT

भाग संख्या 8S89832I
समारोह 1-to-4 Differential-to-LVDS Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8S89832I pdf
8S89832I Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
15, 16
VDD
EN
nIN
VREF_AC
VT
IN
GND
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a
37kpullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. See Table 3A
LVTTL / LVCMOS interface levels.
Inverting differential clock input. 50internal input termination to VT.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting differential clock input. 50internal input termination to VT.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc
2
Revision A January 27, 2016

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