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8S89831I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Differential LVPECL-To-LVPECL/ECL Fanout Buffer - IDT

भाग संख्या 8S89831I
समारोह Differential LVPECL-To-LVPECL/ECL Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8S89831I pdf
8S89831I Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
7, 14
8
9
10
11
12
13
15, 16
Vcc
EN
nIN
VREF_AC
VT
IN
VEE
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Power supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN input. Input threshold is VCC/2. Includes a
37kpull-up resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications.
Termination input. IREF_AC (max.) < ±2mA.
Non-inverting LVPECL differential clock input.
RT = 50termination to VT.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2016 Integrated Device Technology, Inc
2
Revision A January 27, 2016

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