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8P73S674 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1.8V LVPECL Clock Divider - IDT

भाग संख्या 8P73S674
समारोह 1.8V LVPECL Clock Divider
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8P73S674 pdf
8P73S674 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
Name
nIN
NC
VT
IN
N0
GND
N1
8 nOEB
9 nQ3
10 Q3
11 VCC
12 Q2
13 nQ2
14 Q1
15 nQ1
16 VCC
17 Q0
18 nQ0
19 nOEA
20 GND
EPAD
GND_EP
Type
Input
Unused
——
Input
Input
Pulldown
Power
Input
Pulldown
Input
Pulldown
Output
Output
Power
Output
Output
Output
Output
Power
Output
Output
Input
Pulldown
Power
Power
Description
Clock signal inverting differential input. Internal termination 50to VT.
Not connected.
Leave open if IN, nIN is used with LVDS signals.
Clock signal non-inverting differential input. Internal termination 50to VT.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Output enable control for the Q1, Q2 and Q3 outputs.
1.8V LVCMOS/LVTTL interface levels.
Differential clock output 3. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 2. 1.8V LVPECL output levels.
Differential clock output 1. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 0. 1.8V LVPECL output levels.
Output enable control for the Q0 output.
1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Exposed package pad negative supply voltage (GND).
Return current path for the Q0, Q1, Q2 and Q3 outputs.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
1.8V LVPECL CLOCK DIVIDER
2
REVISION 1 12/17/14

विन्यास 15 पेज
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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
8P73S6741.8V LVPECL Clock DividerIDT
IDT


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