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8P34S2102 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Dual 1:2 LVDS Output 1.8V Fanout Buffer - IDT

भाग संख्या 8P34S2102
समारोह Dual 1:2 LVDS Output 1.8V Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=8P34S2102?> डेटा पत्रक पीडीएफ

8P34S2102 pdf
Pin Assignments
Figure 1. Pin Assignments for 3mm x 3mm VFQFN Package – Top View
 
12 11 10
QB0 13
9
8 VREF
nQB0 14
QB1 15
8P34S2102
8XXXXXX
7 nCLKA
6 CLKA
nQB1 16
5 VDD
12 3 4
8P34S2102 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type[a]
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ePad
GND
SELA
CLKB
nCLKB
VDD
CLKA
nCLKA
VREF
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
GND_EPAD
Power
Input (PU)
Input (PD)
Input (PD/PU)
Power
Input (PD)
Input (PD/PU)
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power supply ground.
Control input. Output amplitude select.
Non-inverting differential clock/data input for channel B.
Inverting differential clock/data input for channel B.
Power supply pin.
Non-inverting differential clock/data input for channel A.
Inverting differential clock/data input for channel A.
Bias voltage reference for CLKA, nCLKA and CLKB, nCLKB input pairs.
Differential output A0. LVDS interface levels.
Differential output A0. LVDS interface levels.
Differential output A1. LVDS interface levels.
Differential output A1. LVDS interface levels.
Differential output B0. LVDS interface levels.
Differential output B0. LVDS interface levels.
Differential output B1. LVDS interface levels.
Differential output B1. LVDS interface levels.
Exposed pad of package. Connect to ground.
[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.
See Table 4, DC Input Characteristics, for typical values.
©2017 Integrated Device Technology, Inc.
2
September 21, 2017

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