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DAC8841 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS TrimDAC - Analog Devices

भाग संख्या DAC8841
समारोह CMOS TrimDAC
मैन्युफैक्चरर्स Analog Devices 
लोगो Analog Devices लोगो 
पूर्व दर्शन
1 Page
		
<?=DAC8841?> डेटा पत्रक पीडीएफ

DAC8841 pdf
DAC-8841 -SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: VoD = +5 V, All V,nX = +1.5 V, VrefL = OV, = -AO^C to +85®C apply for DAC-
8841 F, unless otherwise noted.
Parameter
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Half-Scale Output Voltage
Zero-Scale Output Voltage
Output Voltage Drift
SIGNAL INPUTS
Input Voltage Range
Input Resistance
Input Capacitance
REF Low Resistance
REF Low Capacitance
DAC OUTPUTS
Voltage Range
Output Current
Capadtive Load
DYNAMIC PERFORMANCE
Multiplying Gain Bandwidth
Slew Rate
Total Harmonic Distortion
Spot Noise Voltage
Output Settling Time
Channel to Channel Crosstalk
Digital Feedthrough
Symbol
N
INL
DNL
Vhs
Vzs
TCVhs
IVR
Rin
On
RrefL
CrefL
OVR
Iqut
GBW
+SR
-SR
THD
Ct
Q
Conditions
Min Typ Max Units
All Specifications Apply for DACs A, B, C,
D, E, F, G, H
Note 1
All Devices Monotonic, Note 1
PR = 0 V, Sets D = 80h
Digital Code = OOh
PR = 0 V, Sets D = SOh
1.475
±1/2
1.500
20
10
±1.5
±1
1.525
100
Bits
LSB
LSB
V
mV
iivrc
Appliesto All Inputs Vn^X or V^EpL
D = 55h; Code Dependent
Code Dependent
D = ABh; Code Dependent
Code Dependent
0 1.5 V
4 10
kn
19 30 pF
0.3 0.75
kn
190 250 pF
Applies to All Outputs VqutX
Rl = 10 kft
AVout < 25mV, Vn^X = I.375V, PR = 0 V
No Oscillation
0
±5
3V
mA
200 pF
Applies to All DACs
VinX = 100mV p-p +1.0 V dc
1
Measured 10% to 90%
AVoutX = +3 V
1.3
AVoutX = -3 V
1.3
VinX = 1 V p-p + 1.0 V dc, D = FFh, f = 1 kHz,
fu = 80 kHz
f = IkHz
±1 LSB Error Band, Sjq to 255io
Measured Between Adjacent Channels, f = 100 kHz 60
VrefL = +1.5 V, D = 0 to FFh
2.5
4.0
2.5
0.01
0.17
3.5
70
6
6
MHz
V/p,s
V/|jis
%
p,V/VHz
|XS
dB
nVs
POWER SUPPLIES
Positive Supply Current
Idd
Power Dissipation
Pdiss
DC Power Supply Rejection Ratio PSRR
Power Supply Range
PSR
PR = OV
PR = OV
Vdd
4.75
19
95
5.00
26
130
0.01
5.25
mA
mW
%/%
V
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
VlH
Vn,
II
Ql
2.4 V
0.8 V
±10 pA
8 pF
Binary
DIGITAL OUTPUT
Logic High
Logic Low
Vqh loH = -0-4 mA
Vol. Uj = 1.6 mA
3.5
0.4
TIMING SPECIFICATIONS
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load-Edge to Next Clock Edge
kw, kx
tos
^DH
tpD
^LD
tpR
tcKLD
^LDCK
80 ns
40 ns
20 ns
120 ns
70 ns
50 ns
30 ns
60 ns
^[NL^d DNL tests do not include operation at codes 0thru 7due to zero-scale output voltage. For bias voltages above 100 mV on VrhfL, INL and DNL are
maintained over all codes.
Specifications subjectto changewithout notice.
-2-

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डाउनलोड[ DAC8841 Datasheet.PDF ]


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