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IDT8T79S818I-08 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer - Integrated Device Technology

भाग संख्या IDT8T79S818I-08
समारोह 1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
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IDT8T79S818I-08 pdf
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
SCLK
Input
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
2
MISO
Output
Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels.
Frequency Divider Reset. When the nRST is released (rising edge), the divided
3
nRST
Input
Pullup
clock outputs are activated and will transition to a high state simultaneously.
See also Timing Diagram. LVCMOS/LVTTL interface levels (“Figure 1. Timing
Diagram”).
4
PCLK
Input
Pulldown Non-inverting differential clock input.
5
nPCLK
Input
Pullup /
Pulldown
Inverting differential clock input. VCC / 2 by default when left floating.
6
OE
Input
Pulldown
Default output disable. LVCMOS/LVTTL interface levels. See “Table 3B. OE
Truth Table”.
7, 10, 16,
25, 31
VCC
Power
Power supply voltage pin.
8
LE
Input
Pulldown
Serial Control Port Mode Load Enable. Latches data when the pin gets a high
level. Outputs are disabled when LE is low. LVCMOS/LVTTL interface levels.
9 PWR_SEL
Pulldown Power supply selection. See “Table 3A. PWR_SEL Truth Table”.
11, 12
nQD1, QD1
Output
Differential output pair Bank D, output 1. LVPECL or LVDS interface levels.
13, 14
nQD0, QD0
Output
Differential output pair Bank D, output 0. LVPECL or LVDS interface levels.
15, 26
17, 18
VEE
nQC1, QC1
Power
Output
Negative power supply pins.
Differential output pair Bank C, output 1. LVPECL or LVDS interface levels.
19, 20
nQC0, QC0
Output
Differential output pair Bank C, output 0. LVPECL or LVDS interface levels.
21, 22
nQB1, QB1
Output
Differential output pair Bank B, output 1. LVPECL or LVDS interface levels.
23, 24
nQB0, QB0
Output
Differential output pair Bank B, output 0. LVPECL or LVDS interface levels.
27, 28
nQA1, QA1
Output
Differential output pair Bank A, output 1. LVPECL or LVDS interface levels.
29, 30
nQA0, QA0
Output
Differential output pair Bank A, output 0. LVPECL or LVDS interface levels.
32
SDATA
Input
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See “Table 2. Pin Characteristics” for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
ROUT
Output Impedance MISO
Test Conditions
VCC = 3.3V
VCC = 2.5V
Minimum
Typical
2
51
51
125
145
Maximum
Units
pF
k
k
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
2
©2013 Integrated Device Technology, Inc.

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